The patent abstract shows that the present invention relates to the field of MOS semiconductor technology and discloses a SiC VDMOSFET structure capable of reducing parasitic charges, comprising several parallel MOS cell structures. The MOS cell structure comprises a substrate layer, a diffusion layer, a P-body region, and an N-body region; Among them, the bottom ohmic connection of the MOS cell structure has a drain; The P-body region includes lightly doped P-well 1, heavily doped P-well 1, lightly doped P-well 2, heavily doped P-well 2, heavily doped P-well 3, and lightly doped P-well 3, wherein the heavily doped P-well 3 and lightly doped P-well 3 between adjacent MOS cells are integrated. The present invention alternately arranges the regions of strong and weak charge conductivity in the P body region, so that after the gate is connected to the gate voltage and a channel is formed, the other end of the P body region can reduce the concentration of stacking at the other end of the P body region due to this alternating design, thereby improving the stability of the MOS semiconductor after conduction.