At the end of last year, it was reported in the semiconductor supply chain that TSMC's 2nm trial production yield exceeded 60%, which was better than expected, and mass production was scheduled for 2025. A netizen claiming to be an employee of TSMC pointed out on a social media platform that TSMC is expanding its 2-nanometer production capacity, with the goal of producing over 100000 pieces per month.

  This newspaper previously disclosed that TSMC's 2nm adopts a nanosheet architecture for the first time, which has a higher and more complex technological threshold than the current 3-nanometer FinFET process technology; At present, a risk trial production is being carried out at the first factory of Zhuke Baoshan. When the yield reaches the level of mass production, the mass production experience will be replicated to the first factory in Kaohsiung for mass production.

  TSMC does not disclose the yield rate of the trial production, but only emphasizes that the progress of the 2 nanometer technology is smooth and it will be mass-produced as scheduled in 2025, which will be the most leading technology in the industry. The semiconductor supply chain has reported that TSMC's 2-nanometer trial production yield has exceeded 60%, which is better than expected.

  In addition to TSMC, Samsung and Intel are also making efforts in 2nm.

  According to well-known analysis firm TechInsights, Intel's 18A can provide higher performance, while TSMC's N2 may provide higher transistor density. TechInsights analysts believe that TSMC's N2 provides a high-density (HD) standard cell transistor density of 313 MTr/mm2, far exceeding the HD cell densities of Intel 18A (238 MTr/mm2) and Samsung SF2/SF3P (231 MTr/mm2). Although this information roughly matches the SRAM cell sizes of 18A, N2, and N3, as well as TSMC's expectations for N2 and N3, there are still some things to note.

  Firstly, this only involves HD standard units. Almost all modern high-performance processors that rely on cutting-edge nodes use a hybrid of high-density (HD), high-performance (HP), and low-power (LP) standard cells, not to mention features like TSMC's FinFlex and NanoFlex.

  Secondly, it is currently unclear how Intel and TSMC compare their HP and LP standard cells. Although it can be reasonably assumed that N2 leads in transistor density, its leading advantage may not be as significant as HD standard cells. Thirdly, in the papers published at the IEDM event, both Intel and TSMC disclosed the performance, power, and transistor density advantages of their next-generation 18A and N2 manufacturing processes compared to their predecessors. However, there is currently no way to make a positive comparison between these two manufacturing technologies.

  In terms of performance, TechInsights believes that Intel's 18A will lead TSMC's N2 and Samsung's SF2 (formerly known as SF3P). However, TechInsights used a controversial approach to compare the performance of upcoming nodes, as it used TSMC's N16FF and Samsung's 14nm process technology as benchmarks, and then added the node to node performance improvements announced by both companies to make predictions. Although this may be an estimate, it may not be entirely accurate.

  On the other hand, Intel focuses on manufacturing high-performance processors, so the 18A can be tailored for performance and power efficiency, rather than HD transistor density. Ultimately, the 18A supports the back power supply network PowerVia, and chips using this network may have performance and transistor density advantages over TSMC N2, which does not support this feature. However, this does not mean that every 18A chip will use PowerVia.

  When it comes to power consumption, TechInsights analysts speculate that N2 based chips will consume less electricity than similar ICs based on SF2, as TSMC has been leading in power efficiency in recent years. As for Intel, it remains to be seen, but at least the 18A will provide an advantage in this regard.

  Another widely circulated figure is that the price per wafer for TSMC's 2nm process will reach $30000.

  TechInsights provides globally leading semiconductor cost and price models. Before 3nm was put into production, we expected the cost per wafer to be less than $20000. Some customers contacted us, insisting that the price for 3nm was between $20000 and $25000 per wafer. After 3nm was put into production, we were able to obtain proprietary evidence of TSMC's financial situation and confirm that we were correct. The bulk price was below $20000 per wafer, with a difference of thousands of dollars.

  From a price of less than $20000 per 3nm wafer to $30000 per 2nm wafer, it means that the price has increased by more than 1.5 times, the density has also increased by 1.15 times, and the cost of transistors has significantly increased. This raises a question: who will pay for this cost? Our estimated price is less than $30000 per piece. There are also reports that Apple is usually TSMC's main customer for each node, and may abandon the initial 2nm usage due to price reasons, although we have also heard opposition voices.

  Another element of this discussion is that TSMC's bulk wafer prices are much lower than those of small batch wafers, so batch production needs to be considered in any discussion. Overall, we believe that $30000 is higher than the average to bulk pricing.

  If TSMC sets the price of 2nm wafers at $30000 per wafer, they will bring great pressure to customers, forcing them to turn to Intel and Samsung for 2nm level wafer supply